Newer intelligent verification tools are able to derive the essential functions one would expect of a testbench (stimulus, coverage, and checking) from a single, compact, high-level model.
Using a single model that represents and resembles the original specification greatly reduces the chance of human error in the testbench development process that can lead to both missed bugs and false failures.
To counter these problems, in the late 1980s fast logic simulators and specialized hardware description languages such as Verilog and VHDL became popular.
Intelligent verification approaches supplement constrained random simulation methodologies, which bases test generation on external input rather than design structure.
[1] There has been substantial research into the intelligent verification area, and commercial tools that leverage this technique are just beginning to emerge.