Domino logic

Domino logic was developed to speed up circuits, solving the premature cascade problem, typically by inserting static CMOS inverters between domino stages to avoid premature discharge of further cascaded dynamic logic gates.

In CMOS dynamic logic gates, the gate output is precharged to the power supply voltage while the clock is off (the "precharge" phase), and then is evaluated to the correct logic state while the clock is on (the "evaluation" phase) by draining the relevant NMOS transistors in the pull-down network.

The keeper transistor thus connects the dynamic node to the power supply whenever it is supposed to be in the "1" state, allowing the output to be correctly restored despite the charge sharing.

[2] Traditional domino logic circuits are "footed", that is, they have an NMOS transistor controlled by the clock which is connected to the ground rail.

Some domino logic circuits, however, are "footless": they lack this transistor, resulting in higher speed at the cost of greater power leakage.