SPEF is used for delay calculation and ensuring signal integrity of a chip which eventually determines its speed of operation.
The specification for SPEF is a part of the 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System.
The latest version of SPEF is part of 1481-2019 IEEE Standard for Integrated Circuit (IC) Open Library Architecture (OLA) .
SPEF (Standard Parasitic Exchange Format) is documented in chapter 9 of IEEE 1481-1999.
To reduce file size, SPEF allows long names to be mapped to shorter numbers preceded by an asterisk.
This will make SPEF easier to read, but greatly increase file size.
A connection to a top level port starts with a *P. The syntax of the *CONN entries is: Where: The *CAP section provides detailed capacitance information for the net.
It is up to the parasitic extraction and delay calculation flow to decide which corner this value represents.
The acronyms stand for: SPF is a Cadence Design Systems standard for defining netlist parasitics.
In contrast, DSPF models a detailed network of RC parasitics for every net.
SPEF is an Open Verilog Initiative (OVI) — and now IEEE — format for defining netlist parasitics.
SPEF also has a syntax that allows the modeling of capacitance between different nets, so it is used by the PrimeTime SI (crosstalk) analysis tool.
SPEF is smaller than SPF and DSPF because the names are mapped to integers to reduce file size.