Timing closure

and sequential logic gates (flip flops, latches, memories) is modified to meet its timing requirements.

This might improve the performance but increases the total latency (maximum number of registers from input to output path) of the circuit.

The term is also used for the goal that is achieved, when such a design has reached the end of the flow and its timing requirements are satisfied.

IC Compiler by Synopsys, SoC Encounter by Cadence Design Systems and Blast Fusion by Magma Design Automation are examples of tools capable of timing-aware placement, clock tree synthesis and routing and therefore used for physical timing closure.

When the user requires the circuit to meet exceptionally difficult timing constraints, it may be necessary to utilize machine learning[1] programs, such as InTime by Plunify, to find an optimum set of FPGA synthesis, map, place and route tool configuration parameters that ensures the circuit will close timing.