Blackfin
[1] It was designed for a unified low-power processor architecture that can run operating systems while simultaneously handling complex numeric tasks such as real-time H.264 video encoding.
This allows the processor to execute up to three instructions per clock cycle, depending on the level of optimization performed by the compiler or programmer.
Two nested zero-overhead loops and four circular buffer DAGs (data address generators) are designed to assist in writing efficient code requiring fewer instructions.
Other applications use the RISC features, which include memory protection, different operating modes (user, kernel), single-cycle opcodes, data and instruction caches, and instructions for bit test, byte, word, or integer accesses and a variety of on-chip peripherals.
The ISA is designed for a high level of expressiveness, allowing the assembly programmer (or compiler) to optimize an algorithm for the hardware features present.
The L1 internal SRAM memory, which runs at the core-clock speed of the device, is based on a Harvard architecture.
The processors typically have a dedicated DMA channel for each peripheral, which is designed for higher throughput for applications that can use it, such as real-time standard-definition (D1) video encoding and decoding.
The MPU allows Blackfin to support operating systems, RTOSs and kernels like ThreadX, μC/OS-II, or NOMMU Linux.
The official guidance from ADI on how to use the Blackfin in non-OS environments is to reserve the lowest-priority interrupt for general-purpose code so that all software is run in supervisor space.
This variable length opcode encoding is designed for code density equivalence to modern microprocessor architectures.
The newer toolchain is CrossCore Embedded Studio, which uses supports all Blackfin and Blackfin+ processors using upgraded versions of the same compiler and tools internally, but with a UI based on Eclipse CDT.
Other options include Green Hills Software's MULTI IDE and the GNU GCC Toolchain for the Blackfin processor family.
