If a signal does not assert long enough and is not registered, it may appear asynchronous on the incoming clock boundary.
[2] In early computers, typically all the digital logic ran in a single clock domain.
Because of transmission line loss and distortion it is difficult to carry digital signals above 66 MHz on standard PCB traces (the clock signal is the highest frequency in a synchronous digital system), CPUs that run faster than that speed invariably are single-chip CPUs with a phase-locked loop (PLL) or other on-chip oscillator, keeping the fastest signals on-chip.
Synchronizing a single bit signal traversing into clock domain with a slower frequency is more cumbersome.
[5] Other potential clock domain crossing design errors include glitches and data loss.