FPGA prototyping

Procedural recommendations include adding DFP conventions to RTL coding standards, employing a prototype compatible simulation environment, and instituting a system debug strategy jointly with the software team.

Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing.

[6] These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA.

[8] This introduces new challenges for the engineer since manual partitioning requires tremendous effort and frequently results in poor speed (of the design under test).

Various FPGA resources include lookup tables (LUTs), D flip-flops, block RAMs, digital signal processors (DSPs), clock buffers, etc.

A typical problem that arises with creating balanced partitions is that it may lead to timing or resource conflict if the cut is on many signal lines.

In order to achieve optimal place and routing for partitioned designs, the engineer must focus on FPGA pin count and inter-FPGA signals.

If a bug is not able to be captured by the original set of probes, gaining access to additional signals results in a “go home for the day” situation.

[15] EXOSTIV uses large external storage and gigabit transceivers to extract deep traces from FPGA running at speed.

This enables exploring extended debugging scenarios that can't be reached by traditional embedded instrumentation techniques.