NMOS logic

This inversion layer, called the n-channel, can conduct electrons between n-type source and drain terminals.

NMOS was preferred for components that performed active processing such as CPUs or graphics processors due to its higher speed and cheaper manufacturing cost as these were expensive compared to a passive component such as a memory chip, and some chips such as the Motorola 68030 were hybrids with both NMOS and CMOS sections.

MOS stands for metal-oxide-semiconductor, reflecting the way MOS-transistors were originally constructed, predominantly before the 1970s, with gates of metal, typically aluminium.

Since around 1970, however, most MOS circuits have used self-aligned gates made of polycrystalline silicon, a technology first developed by Federico Faggin at Fairchild Semiconductor.

The MOSFETs are n-type enhancement mode transistors, arranged in a so-called "pull-down network" (PDN) between the logic gate output and negative supply voltage (typically the ground).

A pull up (i.e. a "load" that can be thought of as a resistor, see below) is placed between the positive supply voltage and each logic gate output.

Any logic gate, including the logical inverter, can then be implemented by designing a network of parallel and/or series circuits, such that if the desired output for a certain combination of boolean input values is zero (or false), the PDN will be active, meaning that at least one transistor is allowing a current path between the negative supply and the output.