Dynamic logic (digital electronics)

It is distinguished from the so-called static logic by exploiting temporary storage of information in stray and gate capacitances.

[1] It was popular in the 1970s and has seen a recent resurgence in the design of high-speed digital electronics[citation needed], particularly central processing units (CPUs).

Dynamic logic circuits are usually faster than static counterparts and require less surface area, but are more difficult to design.

But there are also differences in usage; the clock can be stopped in the appropriate phase in a system with dynamic logic and static storage.

As a side note, there is, of course, an exception in this definition in the case of high impedance outputs, such as a tri-state buffer; however, even in these cases, the circuit is intended to be used within a larger system where some mechanism will drive the output, and they do not qualify as distinct from static logic.

In the most common version of this concept, the output is driven high or low during distinct parts of the clock cycle.

While there are other mechanisms to do this, such as interrupts, polling loops, processor idling input pins (for example, RDY on the 6502), or processor bus cycle extension mechanisms such as WAIT inputs, using hardware to gate the clock to a static-core CPU is simpler, is more temporally precise, uses no program code memory, and uses almost no power in the CPU while it is waiting.

The hardware logic must gate the latch control inputs as necessary to ensure that a latch output transition does not cause the clock signal level to instantaneously change and cause a clock pulse, either high or low, that is shorter than normal.

Dynamic logic can be harder to work with, but it may be the only choice when increased processing speed is needed.

In the setup phase, the output is driven high unconditionally (no matter the values of the inputs A and B).

Therefore, it is impossible to reduce the idle power consumption (when both inputs are high) below a certain limit derived from an equilibrium between clock speed and load capacitance.