The design and layout of interconnects on an IC is vital to its proper function, performance, power efficiency, reliability, and fabrication yield.
Chemical and mechanical compatibility with the semiconductor substrate and the dielectric between the levels of interconnect is necessary, otherwise barrier layers are needed.
The width and thickness of the interconnect, as well as the material from which it is made, are some of the significant factors that determine the distance a signal may propagate.
Consequently, local interconnects may be formed from materials with relatively high electrical resistivity such as polycrystalline silicon (sometimes silicided to extend its range) or tungsten.
The width, spacing, AR, and ultimately, pitch, are constrained in their minimum and maximum values by design rules that ensure the interconnect (and thus the IC) can be fabricated by the selected technology with a reasonable yield.
As IC structure geometries became smaller, to obtain acceptable yields, restrictions were imposed on interconnect direction.
Initially, only global interconnects were subject to restrictions; were made to run in straight lines aligned east–west or north–south.
Local interconnects, especially the lowest level (usually polysilicon) could assume a more arbitrary combination of routing options to attain the a higher packing density.
The high density of interconnects at the lower levels, along with the minimal spacing, helps support the upper layers.
The bottom-most metal layers of the chip, closest to the transistors, have thin, narrow, tightly-packed wires, used only for local interconnect.
The process used to form DRAM capacitors creates a rough and hilly surface, which makes it difficult to add metal interconnect layers and still maintain good yield.