Interconnect capacitance is calculated by giving the extraction tool the following information: the top view layout of the design in the form of input polygons on a set of layers; a mapping to a set of devices and pins (from a Layout Versus Schematic run), and a cross sectional understanding of these layers.
This information is used to create a set of layout wires that have added capacitors where the input polygons and cross sectional structure indicate.
ANSYS Q3D Extractor uses method of moments (integral equations) and FEMs to compute capacitive, conductance, inductance and resistance matrices.
[citation needed] Source code and Windows binary versions with viewer and editor are freely available from FastFieldSolvers.
[4][5] StarRC from Synopsys (previously from Avanti) is a universal parasitics extractor tool applicable for a full range of electronic designs.