National Semiconductor PACE
National Semiconductor's IPC-16A PACE, short for "Processing and Control Element", was the first commercial single-chip 16-bit microprocessor, announced in late 1974.
[1] It was a single-chip implementation of their early 1973 five-chip IMP-16 architecture, which in turn had been inspired by the Data General Nova minicomputer.
Implemented in pMOS, as was common for the era, PACE required three supply voltages and an external clock with enough signal to drive the internal logic.
This version made electrical interfacing easier and also fixed several bugs in the PACE logic and increased the speed about 50%.
[3] As the external signals were presented at the +8V, interfacing the system with common devices working at TTL levels was not trivial.
This worked in conjunction with the PACE to produce a complete set of bus signals at TTL voltages that could then be used to easily interface with most contemporary devices like SRAM.
For instance, they might be used to indicate that device 6 should present data on the bus, which it might do by mapping 128 bytes of internal buffer onto the split base page mentioned earlier.
[9] This meant that an arbitrary memory location could not be specified directly; several different systems were used to build the required 16-bit address from the 8-bit value.
[9] The idea was that external devices would be mapped onto these high memory locations, and could easily watch for writes and reads by examining the address on the bus and seeing if the top nine bits were all 1's.
[11] Indirect addressing in the PACE was limited, supported primarily by the LD and ST instructions, which load and saved values between the registers and memory.
In dedicated micros, this sort of operation is normally accomplished with several instructions, one that compares the loop index with a given value (in this case, zero), then branches back to the top if the condition is not met.
The PACE's inherent skip-on-zero was a common feature of minis that sped loop performance by avoiding a separate test.
This type of logic has the significant advantage that its internal transistors do not require a large voltage on the substrate layer, like pMOS.
In practical terms, this means an nMOS processor can operate with only two input voltages rather than three, and the positive supply can be set to +5V, making interfacing with TTL circuits trivially easy.
[3] The most important change in terms of usage was that the various signal pins now worked at TTL voltages, allowing them to communicate directly with external systems like memory.
Instead of requiring the relatively complex BTE chip, this task could now be performed by common TTL components, although National Semiconductor suggested their own INS8208 and INS8212 for this purpose.
These changes also allowed the system to run at a higher speed, a 2 MHz crystal was recommended, increasing fairly significantly from the PACE's 1.33.
National Semiconductor suggested either not using this feature, or placing the same address in both locations so they would always call the same code, which would then determine what had actually occurred.
[17] Although the PACE ran at a relatively fast clock speed for the era, the instruction set architecture (ISA) was implemented using microcode and the multiplexed bus required two cycles for each memory access.
As a result, a typical instruction took about 12 to 30 microseconds to complete, making it about the same speed as contemporary 8-bit processors like the Intel 8080.
