Power optimization (EDA)

The complexity of today’s ICs, with over 100 million transistors, clocked at over 1 GHz, means manual power optimization would be hopelessly slow and all too likely to contain errors.

A high absolute level of power is not only undesirable for economic and environmental reasons, but it also creates the problem of heat dissipation.

To respond to this challenge, in the last decade or so, intensive research has been put into developing computed-aided design (CAD) tools that address the problem of power optimization.

Today, most of the research for CAD tools targets system or architectural level optimization, which potentially have a higher overall impact, given the breadth of their application.

The information in these files allow the EDA tools to automatically insert power control features and to check that the result matches the intent.

Several EDA tools have been developed for supporting architectural level power estimation including McPAT,[1] Wattch,[2] and Simplepower.