Semiconductor process simulation

It is a branch of electronic design automation, and part of a sub-field known as technology CAD (TCAD).

Because of the detailed physical modeling involved, process simulation is almost exclusively used to aid in the development of single devices whether discrete or as a part of an integrated circuit.

There are no similar tools available for accurate high resolution measurement of dopant or stress profiles.

For example, back end manufacturing may cause stress in the transistor region changing device performance.

Many of the models were conceived by researchers long before they were needed, but sometimes new effects are only recognized and understood once process engineers discover a problem and experiments are performed.

SUPREM was the resulting software from research by Stanford professor Robert Dutton (engineer).

[3] In 2013, Coventor released SEMulator3D, an advanced process simulator based upon voxel modeling and surface evolution.

[1]: 692  A complete description of FE/FV method is out of the scope of this article but there are many fine books which describe the topic thoroughly.

The accuracy of the profile strongly depends on maintaining a proper density of mesh points at any time during the simulation.

It is important to manage the mesh changes in such a way to avoid accuracy degradation due to interpolation error.

Without careful placement of mesh either the accuracy will suffer unacceptably, or the computational expense will be too great to be useful.

Process simulation tools so far have had limited success in completely automating mesh adaptation such that no user intervention is required.

To include the effects device shape along the depth or to investigate implant shadowing, 3D simulations must be performed.

A result from a simulated semiconductor process. The input is a description of the semiconductor fabrication process; the result as shown here is the final geometry and the concentrations of all the dopants. This will then be used by other programs to predict the electrical properties of the devices formed. (CRC Electronic Design Automation for IC Handbook, Chapter 24)