Its design enables use in mixed-signal integrated circuits for sensor or wireless applications including Bluetooth, Zigbee, GPS, RFID or Near Field Communication chips.
It also includes provisions for modification and adaptation of the technology, establishing a framework for ongoing support, development, and maintenance under specific terms and conditions.
The XAP2, a more advanced microprocessor developed and launched in 1999, incorporated a Harvard architecture and utilized 16-bit data paths, marking a significant improvement over its predecessors.
Additionally, it adopted a more conventional 16-bit instruction width, which enhanced its compatibility with program storage solutions such as Flash and other off-chip memory types, thereby broadening its application in various electronic devices.
XAP2 was adopted by three fabless semiconductor companies that emerged from Cambridge Consultants: CSR plc (Cambridge Silicon Radio) is the main provider of Bluetooth chips for mobile phones and headsets; Ember Corporation is a leading supplier of Zigbee chips; and Cyan Technology supplies XAP2-powered microcontrollers.
As a consequence and combined with other licensees and Cambridge Consultants’ ASIC projects, there are now over one billion (1,000 million) XAP processors in use worldwide.
The XAP3 was the first of Cambridge Consultants’ processors to use a Von Neumann architecture with a logically shared address space for Program and Data.
XAP4 is a very small, 12,000-gate, Von Neumann bus, 16-bit processor core capable of addressing a total of 64 Kbytes of memory for programs, data and peripherals.
It offers high code density combined with good performance in the region of 50 Dhrystone MIPS when clocked at 80 MHz XAP4 was designed for use in modern ASIC or microcontroller applications capable of processing real-world data captured by an analog-to-digital converter (ADC) or similar sources.
This is tailored to the requirements of small, low-energy ASICs as it minimizes processor hardware size (the XAP5 core uses 18,000 gates), and it fits designs that are clocked relatively slowly to reduce an ASIC's dynamic power consumption and run programs direct from Flash or OTP memory that has a slow access time.