This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design.
By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment.
Manually drawn circuit draft schematics of the semiconductor devices made by engineers were transeferred manually onto D-sized vellum sheets by a skilled schematic designer to make a physical layout of the device on a photomask.
[1]: 6 Signoff checks have become more complex as VLSI designs approach 22nm and below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second-order effects.
[3] Since independent tool evaluation is expensive (single licenses for design tools from major vendors like Synopsys and Cadence may cost tens or hundreds of thousands of dollars) and a risky proposition (if the failed evaluation is done on a production design, resulting in a time to market delay), it is feasible only for the largest design companies (like Intel, IBM, Freescale, and TI).