CMOS amplifier
In high performance CMOS (complementary metal–oxide–semiconductor) amplifier circuits, transistors are not only used to amplify the signal but are also used as active loads to achieve higher gain and output swing in comparison with resistive loads.
In the last few decades, to improve speed, power consumption, required area, and other aspects of digital integrated circuits (ICs), the feature size of MOSFET transistors has shrunk (minimum channel length of transistors reduces in newer CMOS technologies).
Progress in memory circuits design is an interesting example to see how process advancement have affected the required size and their performance in the last decades.
In 1956, a 5 MB Hard Disk Drive (HDD) weighed over a ton,[4] while these days[when?]
Novel techniques that achieve higher gain also create new problems, like amplifier stability for closed-loop applications.
The transistor channel length is smaller in modern CMOS technologies, which makes achieving high gain in single-stage amplifiers very challenging.
In contrast, it has limited output swing and difficulty in implementation of unity-gain buffer.
Although FC has lower gain and bandwidth, it can provide a higher output swing, an important advantage in modern CMOS technologies with reduced supply voltage.
Also, since the DC voltage of input and output nodes can be the same, it is more suitable for implementation of unity-gain buffer.
As an example, FC is used as the input stage of a two-stage amplifier in designing of a potentiostat circuit, which is to measure neuronal activities, or DNA sensing.
TIA can be used in amperometric biosensors to measure current of cells or solutions to define the characteristics of a device under test[12] In the last decade[when?
[13] Recently, RFC amplifier has used in hybrid CMOS–graphene sensor array for subsecond measurement of dopamine.
In some applications, like switched capacitor circuits, the value of capacitive load changes in different cycles.
Therefore, it affects output node time constant and amplifier frequency response.
Designer should ensure that phase margin (PM) of the circuit is enough for the worst case.
To have proper circuit behavior and time response, designers usually consider a PM of 60 degrees.
[3] Since capacitive load connected to output nodes, its value affects the location of the dominant pole.
This figure shows how capacitive load affects the location of dominant pole
Increasing capacitive load moves the dominant pole toward the origin, and since unity gain frequency
In some applications, like switched capacitor filters or integrators, and different types of analog-to-digital converters, having high gain (70-80 dB) is needed, and achieving the required gain sometimes is impossible with single-stage amplifiers.
[6] This is more serious in modern CMOS technologies, which transistors have smaller output resistance due to shorter channel length.
The main goal of compensation network is to modify transfer function of the system in such a way to achieve enough PM.
[2][3] So, by the use of compensation network, we should get frequency response similar to what we showed for single-stage amplifiers.
In single-stage amplifiers, capacitive load is connected to the output node, which dominant pole happens there, and increasing its value improves PM.
The following figure shows the block diagram of a two-stage amplifier in fully differential and single ended modes.
Therefore, unlike single-stage amplifiers, increasing of capacitive load, moves the non-dominant pole to lower frequency and deteriorates PM.
The simplest way for compensation of two-stage amplifier, as shown in the left block diagram of the below figure, is to connect compensation capacitor at the output of the first stage, and move dominant pole to lower frequencies.
The issue raised from Miller compensation capacitor is introducing right-half plane (RHP) zero, which reduces PM.
As an example, to cancel the effect of RHP zero, nulling resistor can be used in series with compensation capacitor (right block diagram of the below figure).
